Specification of Timing Constraints in VHDL for High-Level Synthesis

نویسندگان

  • P. Eles
  • K. Kuchcinski
  • Z. Peng
  • M. Minea
  • D. Gajski
  • N. Dutt
  • A. Wu
  • S. Lin
  • G. De Micheli
  • U. Lauther
چکیده

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Timing Preserving Interface Transformations for the Synthesis of Behavioural VHDL

As VHDL spreads widely, its usage for abstract modeling and synthesis is limited by the simulation semantics, which necessitates the specification of the interface signal transitions at bit level with exact timing. This paper shows a methodology to model the interface of a behavioural description suited for high level synthesis where different abstraction levels are separated. It shows the tran...

متن کامل

A VHDL Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis*

In the high-level synthesis domain, the integration of user defined RT components in the algorithmic specification plays an important role. The implementation of VHDL models emulating specific functional and timing behavior at the algorithmic level is expensive and time-consuming. Moreover, particular functional and timing behavior can only be implemented at the RT level, e.g. interrupt handlin...

متن کامل

High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware

This paper describes the principles of high level modeling of digital hardware circuits using the Extended Timing Diagrams (ETD) formalism which adds conditions, events, action expressions and particular constraints to traditional timing diagrams. Hierarchy and concurrency are integrated too such that a full top-down design becomes possible, enhancing in the same time the readability. While for...

متن کامل

Post-synthesis back-annotation of timing information in behavioral VHDL

This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing constraints of a design which is synthesized by a high-level synthesis tool. After synthesis the timing information of the design is back-annotated to the original VHDL description which is then used for s...

متن کامل

Timed Event/Level Structures

This paper presents timed event/level(TEL) structures, an extension to timed event-rule structures, which allows the general use of signal levels and timing in the specification of an asynchronous circuit. TEL structures can express true OR causality, as well as language constructs that are very difficult to describe using purely event based specification methods. This flexibility makes it poss...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1994